Recent Activity

• Burgos commented on #haro Looking for ideas to write about #marine #engineering and #offshore #technology including #shipping… https://t.co/kHanUpx4JR
  "I have got so many ideas to write about engineering technology and shipping http://www.ukbesteessays.com/uk_paper_writing websites. Many possible reviews have been listed to write new posts and ideas for all of them."
  • 1 day ago
• Burgos commented on Feeling too bored n lazy to write anything.. Nothing new.. Just a boxship at berth. #humansatsea #marineengineer… https://t.co/wPo14VEeG9
  "This is one of the best article I have feeling too bored and lazy <a href="https://www.researchwritingkings.com/review-of-studymoose-com/">study moose</a> network. That's why? our engineers wants to catch the basic features."
  • 1 day ago
• Burgos just joined the community.
  • Like
  • 1 day ago
• ali ai robotics at kics commented on Taking each day as it comes #engineroom #marineengineer #loving life https://t.co/itvJblfShU
  "http://www.aiobjectives.com/2019/10/31/on-chip-off-chip-memory-storage-in-artificial-intelligence/ chip memory it means when the processor needs some data, instead of fetching it from main memory it fetches it from some component that is installed on processor itself. The data that a processor frequently needs is prefetched from memory to SRAM to decrease the delay or the latency. SRAM is used as on chip storage; its latency rate is less usually single cycle access time and it is considered as a cache for DRAM."
  • 2 days ago
• ali ai robotics at kics commented on World's Largest LNG-powered Containership Launched
  "http://www.aiobjectives.com/2019/10/31/on-chip-off-chip-memory-storage-in-artificial-intelligence/ chip memory it means when the processor needs some data, instead of fetching it from main memory it fetches it from some component that is installed on processor itself. The data that a processor frequently needs is prefetched from memory to SRAM to decrease the delay or the latency. SRAM is used as on chip storage; its latency rate is less usually single cycle access time and it is considered as a cache for DRAM."
  • 2 days ago